`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/06 21:48:53
// Design Name: 
// Module Name: PrjGieGie
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PrjGieGie(
    input           usb_clk_60m,
    input           rst_n,

    input           usb_rxf_n,
    input           usb_txe_n,
    output reg      usb_oe_n,
    output reg      usb_rd_n,
    output reg      usb_wr_n,
    input [7:0]     usb_data,
    output          usb_siwu_n,

    output          da_clk_1,
    output [9:0]    da_data_1,
    output          da_clk_2,
    output [9:0]    da_data_2
    );

localparam IDLE = 4'b001;
localparam READ = 4'b010;
localparam WRITE = 4'b100;

reg[9:0] da_data;
reg[2:0] cur_state;
reg[2:0] nxt_state;
reg usb_oe_n_d1;

assign da_data_1 = da_data;
assign da_data_2 = 10'b1111111111 - da_data;
assign da_clk_1 = ~usb_clk_60m;
assign da_clk_2 = ~usb_clk_60m;
assign usb_siwu_n = 1'b1;


ila_0 u_ila_0 (
	.clk(usb_clk_60m),

	.probe0(usb_data),  // input wire [7:0]  probe0  
	.probe1(da_data_1), // input wire [9:0]  probe1 
	.probe2(da_data),   // input wire [9:0]  probe2 
	.probe3(da_clk_1),  // input wire [0:0]  probe3 
	.probe4(usb_oe_n),  // input wire [0:0]  probe4 
	.probe5(usb_rd_n),  // input wire [0:0]  probe5 
	.probe6(usb_rxf_n), // input wire [0:0]  probe6 
    .probe7(usb_rxf_n)  // input wire [0:0]  probe7
);  

always@(posedge usb_clk_60m or negedge rst_n) begin
    if (!rst_n)
        usb_oe_n <= 1'b1;
    else if (!usb_rxf_n)
        usb_oe_n <= 1'b0;
    else
        usb_oe_n <= 1'b1;
end

always@(posedge usb_clk_60m or negedge rst_n) begin
    if (!rst_n)
        usb_oe_n_d1 <= 1'b1;
    else
        usb_oe_n_d1 <= usb_oe_n;
end

always@(posedge usb_clk_60m or negedge rst_n) begin
    if (!rst_n)
        cur_state <= IDLE;
    else
        cur_state <= nxt_state;
end

always@(*) begin
    case (cur_state)
    IDLE: begin
        if (usb_rxf_n == 1'b0)
            nxt_state <= READ;
        else
            nxt_state <= IDLE;
    end

    READ: begin
        if ((usb_oe_n_d1 == 1'b1) && (usb_rxf_n == 1'b1))
            nxt_state <= IDLE;
        else
            nxt_state <= READ;
    end

    default:
        nxt_state <= IDLE;
    endcase
end

always@(*) begin
    case (cur_state)
    IDLE: begin
        usb_rd_n <= 1'b1;
        usb_wr_n <= 1'b1;
    end

    READ: begin
        usb_wr_n <= 1'b1;
        if ((usb_oe_n_d1 == 0) && (usb_oe_n == 0))
            usb_rd_n <= 1'b0;
        else
            usb_rd_n <= 1'b1;
        if ((usb_oe_n_d1 == 0) && (usb_rxf_n == 0))
            da_data <= (usb_data <<< 2);
    end

    default: begin
        usb_rd_n <= 1'b1;
        usb_wr_n <= 1'b1;
    end
    endcase
end

endmodule
